CVE-2022-50370: i2c: designware: Fix handling of real but unexpected device interrupts

In the Linux kernel, the following vulnerability has been resolved:

i2c: designware: Fix handling of real but unexpected device interrupts

Commit c7b79a752871 ("mfd: intel-lpss: Add Intel Alder Lake PCH-S PCI IDs") caused a regression on certain Gigabyte motherboards for Intel Alder Lake-S where system crashes to NULL pointer dereference in i2cdwxfermsg() when system resumes from S3 sleep state ("deep").

I was able to debug the issue on Gigabyte Z690 AORUS ELITE and made following notes:

- Issue happens when resuming from S3 but not when resuming from "s2idle" - PCI device 00:15.0 == i2cdesignware.0 is already in D0 state when system enters into pcipmresumenoirq() while all other i2cdesignware PCI devices are in D3. Devices were runtime suspended and in D3 prior entering into suspend - Interrupt comes after pcipmresumenoirq() when device interrupts are re-enabled - According to register dump the interrupt really comes from the i2cdesignware.0. Controller is enabled, I2C target address register points to a one detectable I2C device address 0x60 and the DWICRAWINTRSTAT register STARTDET, STOPDET, ACTIVITY and TXEMPTY bits are set indicating completed I2C transaction.

My guess is that the firmware uses this controller to communicate with an on-board I2C device during resume but does not disable the controller before giving control to an operating system.

I was told the UEFI update fixes this but never the less it revealed the driver is not ready to handle TXEMPTY (or RXFULL) interrupt when device is supposed to be idle and state variables are not set (especially the dev->msgs pointer which may point to NULL or stale old data).

Introduce a new software status flag STATUSACTIVE indicating when the controller is active in driver point of view. Now treat all interrupts that occur when is not set as unexpected and mask all interrupts from the controller.