CVE-2026-89915: KVM: arm64: Remove VM-wide VNCR mapping counter
In the Linux kernel, the following vulnerability has been resolved:
KVM: arm64: Remove VM-wide VNCR mapping counter
The global VNCR mapping counter is used to decide whether an L1 provided VNCR page is mapped in L0 on any CPU at the point of dealing with a TLB invalidation. It is incremented when a mapping is made in the fixmap, and decremented when unmapped.
As it turns out, this tracking has several flaws:
- we are trying to invalidate TLBs, and the mapping is only an opportunistic consequence of the TLB. Checking this counter to decide whether a TLB needs to be invalidated may result in missed invalidations.
- an L1 vcpu invalidating its own TLB (a very likely case) will not succeed in invalidating the VNCR pseudo TLB because that page is not mapped in L0 at this stage.
Given that this tracking fails at delivering the minimum guarantees that are required and is only a performance optimisation, remove it completely.
Remediation
Recommended actions to resolve this vulnerability, in priority order.
- Upgrade
Upgrade
Linux kernel (KVM: arm64)to a version that resolves this vulnerability.Patch KVM: arm64: Remove VM-wide VNCR mapping counter
Event History
Frequently Asked Questions
Which systems are exposed to this issue?
The issue concerns the Linux kernel's KVM implementation on arm64, specifically nested-virtualization handling involving an L1-provided VNCR page. Systems not using KVM on arm64 are not described as affected by the provided information.
What condition can lead to the incorrect behavior?
The problem occurs during TLB invalidation handling when the VM-wide VNCR mapping counter is used to determine whether invalidation is needed. In particular, an L1 vCPU invalidating its own TLB may fail to invalidate the VNCR pseudo-TLB because the page is not mapped in L0 at that time.
What does the fix change?
The fix removes the VM-wide VNCR mapping counter rather than relying on it to decide whether TLB invalidation is required. The counter was only a performance optimization and could cause missed invalidations.