CVE-2026-97515: i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845
i3c: master: svc: Prevent IRQ storm from false SLVSTART on NPCM845
Affected Software
Remediation
Recommended actions to resolve this vulnerability, in priority order.
- Compensating control
In the Linux kernel SVC I3C master handler, when SVC_I3C_QUIRK_FALSE_SLVSTART is set, explicitly clear the SLVSTART status bit after emitting the STOP condition for a Master Request IBI to prevent the IRQ storm on NPCM845.
Event History
Frequently Asked Questions
Which systems are realistically exposed to this issue?
Systems using the Linux kernel I3C SVC master driver on NPCM845 hardware are exposed when an I3C target can become stuck holding SDA low. The false SLVSTART behavior is tied to the SVC_I3C_QUIRK_FALSE_SLVSTART hardware quirk.
What condition triggers the CPU lockup?
A target holding SDA low can cause the controller to report a false Master Request in-band interrupt. The driver's recovery STOP can then spuriously reassert SLVSTART, creating an endless interrupt-handling loop that produces an IRQ storm and can lock up the CPU.
What is the mitigation if the fix cannot be applied immediately?
The provided information identifies the triggering condition as an I3C target stuck holding SDA low. No configuration-only workaround is specified; avoiding or correcting the affected bus/device fault is the only mitigation described by the available data.
How does the fix prevent the repeated interrupts?
After issuing the recovery STOP for a Master Request event, the driver explicitly clears the SLVSTART status bit when the false-SLVSTART quirk is present. This breaks the STOP-to-SLVSTART feedback loop while leaving normal SLVSTART handling unchanged.