RHSA-2020:2842: Moderate: microcode_ctl security, bug fix and enhancement update

First published: Tue Jul 07 2020(Updated: )

Security Fix(es):<br><li> hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)</li> <li> hw: L1D Cache Eviction Sampling (CVE-2020-0549)</li> <li> hw: Vector Register Data Sampling (CVE-2020-0548)</li> For more details about the security issue(s), including the impact, a CVSS<br>score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.<br>Bug Fix(es):<br><li> Update Intel CPU microcode to microcode-20200609 release:</li> <li> Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f</li> up to 0x621;<br><li> Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718</li> up to 0x71a;<br><li> Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;</li> <li> Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e</li> up to 0x2f;<br><li> Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25</li> up to 0x26;<br><li> Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;</li> <li> Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21</li> up to 0x22;<br><li> Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6</li> up to 0xdc;<br><li> Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151</li> up to 0x1000157;<br><li> Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode</li> (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065<br> up to 0x2006906;<br><li> Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c</li> up to 0x4002f01;<br><li> Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c</li> up to 0x5002f01;<br><li> Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6</li> up to 0xdc;<br><li> Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46</li> up to 0x78;<br><li> Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode</li> from revision 0xca up to 0xd6;<br><li> Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision</li> 0xca up to 0xd6;<br><li> Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;</li> <li> Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca</li> up to 0xd6;<br><li> Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.</li> <li> Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision</li> 0xdc, use 0xd6 by default.<br><li> Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.</li> <li> Enable 06-55-04 (SKL-SP/X/W) caveat by default.</li> <li> Avoid find being SIGPIPE'd on early "grep -q" exit in the dracut script.</li> <li> Re-generate initramfs not only for the currently running kernel,</li> but for several recently installed kernels as well.<br><li> Change the URL in the intel-microcode2ucode.8 to point to the GitHub</li> repository since the microcode download section at Intel Download Center<br> does not exist anymore.

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