UBUNTU-CVE-2026-98946: Null Pointer Dereference
In the Linux kernel, the following vulnerability has been resolved: drm/vc4: Disable the V3D interrupt across runtime suspend vc4irqdisable() masks the V3D interrupt sources and then calls synchronizeirq() before the V3D is powered down. However, by itself, this is not enough to quiesce the interrupt handler. synchronizeirq() waits for handlers that have already set IRQDIRQINPROGRESS, and for irqchips reporting IRQCHIPSTATEACTIVE. A GIC interrupt chip is able to mark an interrupt active as soon as a CPU acknowledges it, so there these checks cover the whole dispatch path. On RPi 0-3, however, the interrupt controller is ARMCTRL, which has no active state. A CPU that has read the hwirq out of the pending register but has not yet reached handlelevelirq() stays invisible to synchronizeirq(). During a power transition, vc4irq() may therefore run after the power domain is off, where every V3D register read will return 0xdeadbeef. 0xdeadbeef has FLDONE, FRDONE and OUTOMEM set. This problem doesn't trigger NULL pointer dereference issues only because the functions vc4irqfinishbinjob() and vc4irqfinishrenderjob() return early when there is no job pointer, but OUTOMEM is still able to schedule vc4overflowmemwork() after vc4irqdisable() has already cancelled it. Therefore, fix the spurious interrupts by disabling the interrupt line across the PM transition. To preserve the enable/disable balance, move vc4irqinstall() and request the IRQ line disabled before the first runtime resume.
Affected Software
Remediation
Recommended actions to resolve this vulnerability, in priority order.
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ubuntu/linux-realtimeto a version that resolves this vulnerability.Fixed in 7.0.0-43.43.1 - Configuration
Disable the V3D interrupt line across the runtime power-management transition; mask the V3D interrupt sources, call synchronize_irq(), and request the IRQ line disabled before the first runtime resume after moving vc4_irq_install() to preserve enable/disable balance.
drm/vc4 V3D interrupt handling IRQ line enable state during runtime PM transition = disabled
Event History
Frequently Asked Questions
Which systems are exposed to this race condition?
The described gap applies to Raspberry Pi 0 through 3 systems using the ARMCTRL interrupt controller and the VC4/V3D graphics path during runtime power transitions. The issue is not described as applying to GIC-based interrupt controllers, because they report an active interrupt state that synchronize_irq() can observe.
What makes the interrupt synchronization insufficient on affected hardware?
On ARMCTRL, a CPU can have read the hardware interrupt number from the pending register but not yet entered handle_level_irq(). In that interval, the interrupt is not visible as in progress or active to synchronize_irq(), so the VC4 interrupt handler can execute after the V3D power domain has been shut down.